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/*
Enable External XTAL (4~24 MHz)
*/
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
/*
Waiting for 20MHz clock stable
*/
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
/*
Switch HCLK(CPU clock) clock source to XTAL
*/
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT,CLK_CLKDIV0_HCLK(1));
#if 1
/* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/
CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
/* Set PLL frequency */
CLK->PLLCTL = CLK_PLLCTL_84MHz_HXT;
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
/* Switch HCLK clock source to PLL */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL,CLK_CLKDIV0_HCLK(1));
#endif
/*
Enable IP clock
*/
// CLK_EnableModuleClock(UART0_MODULE);
CLK_EnableModuleClock(UART3_MODULE);
CLK_EnableModuleClock(UART4_MODULE);
CLK_EnableModuleClock(TMR0_MODULE);
CLK_EnableModuleClock(SPI0_MODULE);
CLK_EnableModuleClock(USBD_MODULE);
/*
Select IP clock source
*/
// CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1));
CLK_SetModuleClock(UART3_MODULE, CLK_CLKSEL1_UARTSEL_PLL, CLK_CLKDIV0_UART(1));
CLK_SetModuleClock(UART4_MODULE, CLK_CLKSEL1_UARTSEL_PLL, CLK_CLKDIV0_UART(1));
CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HXT, 0);
/* Enable USB PHY */
SYS->USBPHY = 0x100; // USB device
when I close this one " /* Switch HCLK clock source to PLL */",回覆
BokarevSF
PambMadia