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PWM Capture and PWM Output share the same hardware. When a rising edge or a falling edge occurs, the value of a PWM counter will be latched into the corresponding rising or falling latch register. At this time, whether to reload the PWM counter or an interrupt event occurs can be determined.
The PWM Capture is mainly used to measure the input waveform of high level and (or) a high-level pulse width. The following diagram is used as example for illustration:
To measure the time W2 from a rising edge to a falling edge (high level), the user can set the PWM counter reload value CN when a rising edge occurs. A falling latch value CFL can be obtained when a falling edge occurs. The time W2 can be calculated using the following formula:
(CN+1-CFL)*(prescale+1)*(clock divider)/PWM_CLK
Note: prescale: 8-bit prescale
clock divider: divider options
PWM_CLK: PWM clock source frequency
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Applications: | |
Function: | Peripherals,Timer and PWM,PWM-Capture |