VPLL Limitation
Code: Select all
85.7 MHz < VPLL < 2400 MHz
Here is an example in our default setting
We have set the VPLL to 102 MHz because the display timing necessitates a 51 MHz frequency, and the VPLL must be double or four times the pixel clock frequency.
Code: Select all
ma35d1.dtsi
clk: clock-controller@40460200 {
compatible = "nuvoton,ma35d1-clk", "syscon", "simple-mfd";
reg = <0x00000000 0x40460200 0x0 0x100>;
#clock-cells = <1>;
assigned-clocks = <&clk CAPLL>,
<&clk DDRPLL>, <&clk APLL>,
<&clk EPLL>, <&clk VPLL>;
assigned-clock-rates =<1000000000>,
<266000000>, <200000000>,
<500000000>, <102000000>;
clock-pll-mode = <0>, <1>, <0>, <0>, <0>;
nuvoton,sys = <&sys>;
};
display-timings {
native-mode = <&timing0>;
timing0: 1024x600 {
clock-frequency = <51000000>;//pixel clock(pixclock)
hactive = <1024>;
vactive = <600>;
hsync-len = <1>;
hfront-porch = <160>;
hback-porch = <160>;
vsync-len = <1>;
vfront-porch = <23>;
vback-porch = <12>;
hsync-active = <1>;
vsync-active = <1>;
};