This is because the corresponding peripheral interrupt flag in the NVIC_ICPR register has not been cleared.
In the Cortex-M architecture, the order in which interrupt service routine executed is controlled through the NVIC. There are two flags in this issue. One is the internal interrupt flag in the peripheral and the other is the flag in the NVIC that records which peripheral issued the interrupt.
When the peripheral interrupt flag is set to 1, the corresponding value of the NVIC_ICPR register in the NVIC is set to 1. If the user only clears the peripheral interrupt flag, the corresponding value in the NVIC_ICPR register is still set. The program will still enter the interrupt service routine according to the NVIC_ICPR register.
The procedure for entering the interrupt service routine is as follows:
(1) Peripheral interrupts are triggered
(2) The peripheral interrupt flag is raised
(3) In NVIC, the flag corresponding to the NVIC_ICPR register is raised
(4) After NVIC’s scheduling, enter the interrupt service routine.
There are two ways to clear the NVIC_ICPR register.
(1) Automatically cleared by hardware when entering the interrupt service routine.
(2) Manually cleared by software.
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