Adjust LCM clock
From:
// LCD clock is selected from UPLL and divide to 20MHz
outpw(REG_CLK_DIVCTL1, (inpw(REG_CLK_DIVCTL1) & ~0xff1f) | 0xe18);
To:
// LCD clock is selected from UPLL and divide to 20MHz
outpw(REG_CLK_DIVCTL1, (inpw(REG_CLK_DIVCTL1) & ~0xff1f) | 0x918);
Constrain:
Higher FPS will cause bandwidth issue
[NUC972] How to fix Non-OS LCM vibration
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