M487 "turbo" mode

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sittinhawk
Posts: 9
Joined: 23 Jan 2023, 21:28

04 Feb 2024, 19:58

I want to have the M487 CPU core run at maximum frequency (192 MHz). I already have the PLL setup and can get it up to 96 MHz right now, but if I try to go faster the CPU stalls out. Table 6.2-2 of User Manual says 192 MHz is only possible in Turbo mode, but it does not explain what "turbo" mode is and how to enable it. All it mentions is that the LDO_CAP needs to be at 1.26V instead of 1.2V. But it doesn't explain how to change it. I tried to change the LDO_CAP voltage using the SYS_PLCTL register but it did not work (again, no description on what this register does and how to use it).

What are the steps to run the CPU core at 192 MHz?

morgandu
Posts: 45
Joined: 28 Apr 2017, 22:47

05 Feb 2024, 10:35

In M480BSP, all sample code have include system_M480.c. The SystemInit() function (in system_M480.c) which be called before main() will configure LDO to 1.26V. And most SYS_Init() function in main.c have configure PLL to output 192MHz.

If you try sample code in M480BSP, or build your application based on one of M480BSP sample code, the M487 is already run at 192MHz.

sittinhawk
Posts: 9
Joined: 23 Jan 2023, 21:28

05 Feb 2024, 20:48

Thank you, that helped. Looks like the piece I was missing was setting the flash controller cache miss cycles to the appropriate value for the higher frequency. Now I'm am running at 192 MHz. Still didn't exactly see in SystemInit() where the LDO voltage was being changed. Maybe it happens automatically based on settings?

morgandu
Posts: 45
Joined: 28 Apr 2017, 22:47

06 Feb 2024, 09:27

After setting flash cycle, the CLK_LDOCTL register is also set to allow LDO to output 1.26V.

sittinhawk
Posts: 9
Joined: 23 Jan 2023, 21:28

06 Feb 2024, 20:57

Okay, thank you for letting me know that. The user manual describes the single bit in the CLK_LDOCTL register as "DPD (deep power down mode) Wake Up Time Select Bit", so I wasn't able to infer that this bit would change the LDO output to 1.26V.

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