How to achieve the highest sampling frequency when using ADC sampling?

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When using ADC sampling, the ADC has a different clock source frequency limit based on the voltage supplied by AVDD. The user can select the fastest clock source according to the system analog voltage to achieve the maximum ADC sampling frequency.

For example, in the NuMicro? NUC442/472 series:
When AVDD works at 4.5 -5.5V, the highest clock source frequency limit that can be entered is 16 MHz. The users can select the PLL frequency as the clock source, and then obtain the fastest clock source through a divider.
The PLL frequency is set to 80 MHz and divided by 5 through a divider. Accordingly, the clock source that can be obtained is 16 MHz, and the highest ADC sampling frequency achieved is 800 kSPS.