The Timer controller provides One-shot, Periodic, Toggle and Continuous (Auto-reloaded) Counting Operation modes. It also provides the event counting function to count the event from an external pin and the input capture function to capture or reset the timer counter value. (The NUC100/NUC120 medium...

They are 8-bit pre-scaler and 24-bit up-counting timer counter.

The supported external clock sources include 4-24 MHz(HXT), 32.768 kHz(LXT), and GPIO.
The supported internal clock sources include system clock HCLK and internal RC (HIRC).
User can select a different clock source for each Timer controller by setting the TMRx_S bit of CLKSEL1 register.

There are up to 4 sets of 32-bit Timer controllers in a chip of NuMicro® family, but it depends on the part number.
Timer and PWM timer is independent of selecting the clock source.
Hence, user can also use the Systick and the PWM Timer (if PWM Timer enabled but the PWM output disabled) as the Timer.

The only clock source of RTC controller comes from the LXT.
Since the LXT still works in Power-down mode, RTC can operate and wake up the whole chip from this mode.

The NUC100, NUC200, Nano100 and NUC442/NUC472 Series support the RTC controller. The power of RTC controller shares with the power of whole chip for the most chips in NuMicro® family. Once a chip is powered off, the RTC will work incorrectly when the chip is powered on again. Nevertheless, the NUC20...

User can use the UID (Unique ID) to encrypt all the NuMicro family chips except NUC100AN and NUC100BN Series. As to UID (Unique ID), Nuvoton will plant the UID into chips as mentioned above and each chip’s UID is different from others. User can provide some judging rules in the firmware code to prev...

It is 512 bytes per page to erase for Cortex-M0 and 2k bytes for Cortex-M4.
The data size for per data to program is 4 bytes (a word).

Yes, the LOCK bit is provided on the User Configuration Word to protect user's program code. When this LOCK bit is set, all of the data on the Flash memory will be read back as 0xFFFFFFFF. At this time, the "Whole Chip Erase" operation should only be performed for the target chip to unlock the LOCK ...

ISP stands for "In System Programming". The target chip runs the boot/loader code of LDROM through the peripheral interface such as USB/UART/SPI/I2C/RS-485/CAN... to update the internal APROM, Data Flash and User Configuration Word. ISP.png ICP stands for "In Circuit Programming". PC runs the softw...